SPI Flash
π§ SPI Perfect π Here's your English version, translated naturally for an undergraduate + practical level audience β exactly matching the tone and detail of the Korean version you liked.
π§ SPI Flash Command Structure (Based on Winbond W25Q Series)
1οΈβ£ Basic SPI Transaction Structure
Each SPI command frame usually follows this sequence:
[CS LOW] β [Command] β [Address (optional)] β [Data (Read/Write)] β [CS HIGH]
| Step | Description | Example |
| CS LOW | Start communication | Activate the target slave |
| Command (1 byte) | Specifies operation | e.g., 0x9F (Read JEDEC ID) |
| Address (3~4 bytes) | Target location | For read/write operations |
| Data | Transmit or receive data | Data exchange section |
| CS HIGH | End communication | Deactivate slave |
2οΈβ£ Common Commands (W25Q64 Example)
| Hex Code | Command Name | Direction | Description |
0x9F | Read JEDEC ID | Slave β Master | Reads manufacturer and device ID |
0x06 | Write Enable | - | Enables write/erase operations |
0x04 | Write Disable | - | Disables writing |
0x05 | Read Status Register 1 | Slave β Master | Check write-in-progress bit |
0x03 | Read Data | Slave β Master | Normal read operation |
0x0B | Fast Read | Slave β Master | High-speed read (includes dummy byte) |
0x02 | Page Program | Master β Slave | Writes up to 256 bytes per page |
0x20 | Sector Erase (4KB) | Master β Slave | Erases one sector |
0xD8 | Block Erase (64KB) | Master β Slave | Erases one block |
0xC7 / 0x60 | Chip Erase | Master β Slave | Erases the entire chip |
0xB9 | Power Down | - | Enters low power mode |
0xAB | Release Power Down / Read Device ID | Slave β Master | Wake up & read ID |
3οΈβ£ Example Command Sequences
π§© (1) Read JEDEC ID β 0x9F
Used to confirm the Flashβs manufacturer and device type.
| Step | Description | Example |
| CS LOW | Start transaction | |
Send 0x9F | Command | |
| Read 3 bytes | Receive via MISO | EF 40 17 |
| CS HIGH | End transaction |
Result:
Manufacturer ID =
0xEF(Winbond)Memory Type =
0x40Capacity =
0x17β 64 Mbit
π§© (2) Read Data β 0x03
| Step | Description |
| CS LOW | |
Send 0x03 (Read Data command) | |
Send 3-byte address (e.g., 00 10 00) | |
| Read data bytes (via MISO) | |
| CS HIGH |
Example waveform:
MOSI: [03 00 10 00]
MISO: [AA BB CC DD ...] β Flash contents
π§© (3) Page Program β 0x02
You must enable writing before programming.
Step 1: Write Enable
CS LOW
0x06
CS HIGH
Step 2: Page Program
CS LOW
0x02
<Address 3 bytes>
<Data up to 256 bytes>
CS HIGH
Then poll the WIP (Write In Progress) bit via 0x05.
while(ReadStatus() & 0x01); // Wait until WIP == 0
π§© (4) Read Status Register β 0x05
| Step | Description |
| CS LOW | |
0x05 | |
| Read 1 byte | |
| CS HIGH |
| Bit | Name | Description |
| 0 | WIP | Write in progress (1 = busy) |
| 1 | WEL | Write Enable Latch |
| 7 | SRP0 | Status Register Protect |
π§© (5) Sector Erase β 0x20
| Step | Description |
Write Enable (0x06) | |
| CS LOW | |
0x20 | |
| Address (3 bytes, sector start address) | |
| CS HIGH |
Then use 0x05 to check WIP bit until erase completes.
4οΈβ£ MCU-Level Example Code
// Read Flash ID
CS_LOW();
SPI_Transfer(0x9F);
uint8_t mfg = SPI_Transfer(0x00);
uint8_t type = SPI_Transfer(0x00);
uint8_t cap = SPI_Transfer(0x00);
CS_HIGH();
printf("Flash ID: %02X %02X %02X\n", mfg, type, cap);
// Read Data
CS_LOW();
SPI_Transfer(0x03); // Read command
SPI_Transfer(0x00); // Addr[23:16]
SPI_Transfer(0x10); // Addr[15:8]
SPI_Transfer(0x00); // Addr[7:0]
for(int i = 0; i < 16; i++)
buffer[i] = SPI_Transfer(0x00); // Dummy write to read data
CS_HIGH();
5οΈβ£ Typical Operation Flow
1) 0x9F β Read JEDEC ID
=> EF 40 17
2) 0x06 β Write Enable
3) 0x20 + Address β Erase Sector
4) 0x02 + Address + Data β Page Program
5) 0x03 + Address β Read Data
6οΈβ£ Example SPI Waveform (Logic Analyzer View)
CS: ββββββββββ β β β β β β β β β β β β β β β β βββββββββββββ
SCLK: ββββββββββββββββββ
MOSI: 0x9F 00 00 00
MISO: EF 40 17
β This frame represents a βRead JEDEC IDβ transaction.
7οΈβ£ Summary Table
| Category | Description |
| Frame Control | Controlled by CS (Chip Select) |
| Command Structure | Command β Address β Data |
| Write Sequence | Must use 0x06 before write/erase |
| Status Check | Read WIP bit via 0x05 |
| Flash ID | 0x9F β 3-byte ID response |
| Basic Read | 0x03 (normal), 0x0B (fast) |
| Erase Options | 0x20 (4KB), 0xD8 (64KB), 0xC7 (Chip erase) |
π‘ Key Takeaway
SPI Flash communication is command-driven and synchronous.
Each operation begins with pulling CS low,
followed by sending a command and address,
then exchanging data through MOSI/MISO lines.Typical workflow:
Write Enable β Command β Status Check β Read/Write Data
Would you like me to include the waveform timing diagram (with MOSI/MISO/SCLK transitions labeled) next?
It would visually explain how each byte shifts bit-by-bit β excellent for interviews or reports. Command Structure (Based on Winbond W25Q Series)
1οΈβ£ Basic SPI Transaction Structure
Each SPI command frame usually follows this sequence:
[CS LOW] β [Command] β [Address (optional)] β [Data (Read/Write)] β [CS HIGH]
| Step | Description | Example |
| CS LOW | Start communication | Activate the target slave |
| Command (1 byte) | Specifies operation | e.g., 0x9F (Read JEDEC ID) |
| Address (3~4 bytes) | Target location | For read/write operations |
| Data | Transmit or receive data | Data exchange section |
| CS HIGH | End communication | Deactivate slave |
2οΈβ£ Common Commands (W25Q64 Example)
| Hex Code | Command Name | Direction | Description |
0x9F | Read JEDEC ID | Slave β Master | Reads manufacturer and device ID |
0x06 | Write Enable | - | Enables write/erase operations |
0x04 | Write Disable | - | Disables writing |
0x05 | Read Status Register 1 | Slave β Master | Check write-in-progress bit |
0x03 | Read Data | Slave β Master | Normal read operation |
0x0B | Fast Read | Slave β Master | High-speed read (includes dummy byte) |
0x02 | Page Program | Master β Slave | Writes up to 256 bytes per page |
0x20 | Sector Erase (4KB) | Master β Slave | Erases one sector |
0xD8 | Block Erase (64KB) | Master β Slave | Erases one block |
0xC7 / 0x60 | Chip Erase | Master β Slave | Erases the entire chip |
0xB9 | Power Down | - | Enters low power mode |
0xAB | Release Power Down / Read Device ID | Slave β Master | Wake up & read ID |
3οΈβ£ Example Command Sequences
π§© (1) Read JEDEC ID β 0x9F
Used to confirm the Flashβs manufacturer and device type.
| Step | Description | Example |
| CS LOW | Start transaction | |
Send 0x9F | Command | |
| Read 3 bytes | Receive via MISO | EF 40 17 |
| CS HIGH | End transaction |
Result:
Manufacturer ID =
0xEF(Winbond)Memory Type =
0x40Capacity =
0x17β 64 Mbit
π§© (2) Read Data β 0x03
| Step | Description |
| CS LOW | |
Send 0x03 (Read Data command) | |
Send 3-byte address (e.g., 00 10 00) | |
| Read data bytes (via MISO) | |
| CS HIGH |
Example waveform:
MOSI: [03 00 10 00]
MISO: [AA BB CC DD ...] β Flash contents
π§© (3) Page Program β 0x02
You must enable writing before programming.
Step 1: Write Enable
CS LOW
0x06
CS HIGH
Step 2: Page Program
CS LOW
0x02
<Address 3 bytes>
<Data up to 256 bytes>
CS HIGH
Then poll the WIP (Write In Progress) bit via 0x05.
while(ReadStatus() & 0x01); // Wait until WIP == 0
π§© (4) Read Status Register β 0x05
| Step | Description |
| CS LOW | |
0x05 | |
| Read 1 byte | |
| CS HIGH |
| Bit | Name | Description |
| 0 | WIP | Write in progress (1 = busy) |
| 1 | WEL | Write Enable Latch |
| 7 | SRP0 | Status Register Protect |
π§© (5) Sector Erase β 0x20
| Step | Description |
Write Enable (0x06) | |
| CS LOW | |
0x20 | |
| Address (3 bytes, sector start address) | |
| CS HIGH |
Then use 0x05 to check WIP bit until erase completes.
4οΈβ£ MCU-Level Example Code
// Read Flash ID
CS_LOW();
SPI_Transfer(0x9F);
uint8_t mfg = SPI_Transfer(0x00);
uint8_t type = SPI_Transfer(0x00);
uint8_t cap = SPI_Transfer(0x00);
CS_HIGH();
printf("Flash ID: %02X %02X %02X\n", mfg, type, cap);
// Read Data
CS_LOW();
SPI_Transfer(0x03); // Read command
SPI_Transfer(0x00); // Addr[23:16]
SPI_Transfer(0x10); // Addr[15:8]
SPI_Transfer(0x00); // Addr[7:0]
for(int i = 0; i < 16; i++)
buffer[i] = SPI_Transfer(0x00); // Dummy write to read data
CS_HIGH();
5οΈβ£ Typical Operation Flow
1) 0x9F β Read JEDEC ID
=> EF 40 17
2) 0x06 β Write Enable
3) 0x20 + Address β Erase Sector
4) 0x02 + Address + Data β Page Program
5) 0x03 + Address β Read Data
6οΈβ£ Example SPI Waveform (Logic Analyzer View)
CS: ββββββββββ β β β β β β β β β β β β β β β β βββββββββββββ
SCLK: ββββββββββββββββββ
MOSI: 0x9F 00 00 00
MISO: EF 40 17
β This frame represents a βRead JEDEC IDβ transaction.
7οΈβ£ Summary Table
| Category | Description |
| Frame Control | Controlled by CS (Chip Select) |
| Command Structure | Command β Address β Data |
| Write Sequence | Must use 0x06 before write/erase |
| Status Check | Read WIP bit via 0x05 |
| Flash ID | 0x9F β 3-byte ID response |
| Basic Read | 0x03 (normal), 0x0B (fast) |
| Erase Options | 0x20 (4KB), 0xD8 (64KB), 0xC7 (Chip erase) |
π‘ Key Takeaway
SPI Flash communication is command-driven and synchronous.
Each operation begins with pulling CS low,
followed by sending a command and address,
then exchanging data through MOSI/MISO lines.Typical workflow:
Write Enable β Command β Status Check β Read/Write Data