I2C (Inter-Integrated Circuit)
📘 I2C (Inter-Integrated Circuit)
1) Concept
I2C is a two-wire serial communication bus used to connect multiple devices. It is commonly used for sensors, EEPROMs, PMICs, RTCs, touch controllers, and other low-speed peripherals.
SPI: faster, requires more wires (typically 4+)
I2C: slower, but only needs 2 wires
Therefore, I2C is preferred when wiring simplicity is more important than data rate.
2) Bus Signals (Only 2 Lines)
| Signal | Description |
| SCL (Clock) | Clock generated by the master |
| SDA (Data) | Bidirectional data line |
Both lines use open-drain signaling, so pull-up resistors (typically 2.2kΩ–10kΩ) are required.
SCL ────┬─■(Pull-up)─ Vcc
SDA ────┤
3) Roles: Master & Slave
| Role | Description |
| Master | Generates SCL, initiates and terminates communication (usually the MCU) |
| Slave | Responds to master requests (sensors, memory devices, etc.) |
A single I2C bus can have multiple slave devices, each addressed individually.
4) Data Transfer Rules
I2C communication follows this sequence:
START
→ Slave Address (7-bit or 10-bit)
→ R/W bit (0 = Write, 1 = Read)
→ ACK
→ Data (1 byte at a time)
→ ACK after each byte
→ STOP
Important: I2C transfers 1 byte (8 bits) at a time,
and the receiver responds with 1 additional bit:
| Frame Element | Explanation |
| 8 data bits | Sent by master or slave |
| 1 ACK/NACK bit | Sent by the receiver on the 9th clock |
| Response | Bit Level | Meaning |
| ACK | SDA pulled LOW (0) | “Byte received, continue.” |
| NACK | SDA remains HIGH (1) | “Cannot receive more, stop here.” |
Example: Writing value 0xAB to slave 0x50:
START
0x50 + Write(0) → ACK
0xAB → ACK
STOP
5) Speed Modes
| Mode | Data Rate | Usage |
| Standard | 100 kbps | Basic communication |
| Fast | 400 kbps | Common default |
| Fast Plus | 1 Mbps | Higher-speed sensors |
| High-Speed | 3.4 Mbps | Specialized applications |
Compared to SPI/QSPI, I2C is significantly slower.
6) Advantages
Very simple wiring (only two lines)
Easy to add multiple slave devices (address-based)
Low hardware cost (just pull-up resistors)
7) Disadvantages
Slow data rate
Signal integrity can degrade with cable length or noise
Open-drain signaling → less clean waveforms
If ACK/NACK handling fails, the bus may lock up (hang)
Thus, I2C Bus Recovery routines are commonly required in real firmware.
8) Comparison with SPI/QSPI
| Feature | I2C | SPI | QSPI |
| Number of wires | 2 | 4+ | 6 |
| Speed | Slow | Fast | Faster |
| Topology | Multi-slave bus | Point-to-point | Point-to-point |
| Typical usage | Sensors, EEPROM | ADC/DAC, high-speed peripherals | External flash / firmware storage |
| Hardware complexity | Low | Medium | High |
9) One-Line Summary
I2C is a low-speed serial bus that uses only two wires and transfers data one byte at a time,
with the receiver sending an ACK/NACK bit after each byte.